1. Field of the Invention
The present invention relates to a capacitive load driving circuit and a display panel driving circuit. More particularly, the present invention relates to the capacitive load driving circuit and the display panel driving circuit which can improve a display performance.
2. Description of the Related Art
A flat-panel display has been widely known, which can be able to downsize its thickness and weight. The flat-panel display is an indispensable display apparatus for our modern life. Especially, a liquid crystal display (LCD) has been greatly improved in a picture quality, a high resolution and cost-performance because of a result of competitive efforts by enterprises. Generally, the liquid crystal display apparatus is mainly composed of a liquid crystal display panel and a driver IC. It is highly desired to increase the number of display pixels in recent years. Therefore, it is necessary to increase the number of outputs for the driver IC. Responding to this, the downsizing of the chip may be achieved by refining the driver IC design rule. However, a simply downsizing of the chip causes the connection pitch between the driver IC and the display panel to be narrow. This may possibly lead to decrease of the manufacturing yield. Additionally, because drive voltage depends on the property of the liquid crystalline in the display panel, it is hard to lower the voltage considerably to a large degree. Therefore, it is difficult for the output circuit having a large area in the driver IC to adopt the refined design rule as a low-voltage circuit. This means that the downsizing of the chip in the driver IC is impossible and the cost for the driver IC in entire liquid crystal display can not be lowered. This is why the another approach is necessary for the downsizing of the chip.
Japanese Laid Open Patent Application (JP-A-Heisei 4-52684 discloses a technique of a driving method of the Liquid crystal panel to reduce the chip size of the driver IC. In the conventional method, source lines are extended to the Y direction in the liquid crystal panel of an active matrix type. The source lines are arranged in the X direction to be driven by a driver IC. The driver IC has a plurality of data lines, and each of first switching elements is provided in each of the data lines. In addition, each of second switching elements is provided in each source line of the above-mentioned liquid crystal display panel. The outputs of the above-mentioned driver IC connect the plurality of the source lines, which correspond to the data lines, of the liquid crystal display panel. Then, each of the first switching elements of the driver IC is sequentially switched on and off synchronizing with each of the second switching elements of the liquid crystal display panel. Then, the source data from the data line is time-shared to be supplied to the source line corresponding to the above-mentioned data line from the one output of the driver IC. Such configuration of the circuit in the liquid crystal display panel contributes to reduce the circuit scale of the driver IC.
FIG. 1 is a circuit diagram showing a configuration of a driving circuit of the conventional display panel in which the technique in JP-A-Heisei 4-52684 is applied. A driving circuit of the display panel includes a liquid crystal display panel 104 and a driver IC 101. A plurality of data lines 121 and a plurality of gate lines 122 are formed on the liquid crystal display panel 104. Pixels 110 are connected to parts of rectangular grids by these lines. The pixel 110 includes a pixel switch 112 and a liquid crystal cell 111. Six data lines D1 to D6 configure a data line array. One end of each switch element connects with a drive-side end of each data line. The other ends of the switches are commonly connected with each other and connected with an output circuit 102 of the driver IC 101.
The driver IC 101 includes at least a data register 107, a latch 106, and an output circuit 102. The data register 107 sequentially stores digital picture signals of n bits inputted from an outside. When the data register 107 stores digital picture signals for one gate line, then transmits those signals to the latch 106. The latch 106 outputs the stored digital picture signals to the output circuit 102 sequentially. For instance, digital picture signals R1, G1, B1, R2, G2, and B2 of n bits from an outside are stored in the data register 107 sequentially. These signals are transmitted to the latch 106 at the same time. Then, the picture signals R1 G1, B1, R2, G2, and B2 stored in latch 106 are outputted in this order. The output circuit 102 converts the input digital picture signal into analog picture signals, and drives data lines D1 to D6. At this time, the switching elements are selected and turned on in order of 191, 192, 193, 194, 195 and 196 synchronizing with the output timing of the latch 106. The picture signal R1, G1, B1, R2, G2, and B2 are written in the data lines D1 to D6 respectively. The adjoining data line array is also driven in parallel in the similar timing.
The liquid crystal display panel 104 and the pixel 110 are considered as a capacitive load in the light of the driver IC 101. Therefore, the electric charge of the picture signal (hereinafter referred to as the picture signal charge) is stored in each data line by the above-mentioned serial operation. Due to a scanning selection of gate lines 121, the pixel transistor 112 becomes ON state and the picture signal charge is transmitted to the liquid crystal cell 111 respectively, then pixel transistor 112 becomes OFF state after all writing operation in the data lines is completed. As a result, the writing operation of the picture signal in the liquid crystal cell 111 for one gate line is completed.
Due to the above-mentioned configuration, the output circuit 102 can be shared in six data lines. Therefore, it is possible to reduce the scale of the output circuit to one-sixth (⅙) of a usual configuration in this example. As a result, it can be possible to downsize the chip of the driver IC. Moreover, the circuit scale can be reduced by increasing the number of the sharing data lines.
In the above conventional technique, brightness unevenness in a vertical direction (hereinafter referred to as a vertical unevenness) might be highly visible in a single-color halftone display and a two-color halftone display. Here, the single-color halftone display means the display in which brightness of only one of RGB three primary colors composed of a pixel is a halftone. The two-color halftone display means the display in which brightness of two of RGB three primary colors is a halftone. The vertical unevenness indicates an unevenness of dark and light in brightness appearing in the direction parallel to the gate line.
Unevenness in the display such as the vertical unevenness occurs by a change of the picture signal voltage maintained in the data line 121 when the picture signal is the written to the liquid crystal cell 111. One of the reasons of this voltage change is that the writing electric charge in the data line 121 is released toward the driver IC 101 due to the leakage current of the switching elements 191 to 196. It should be noted that the switching elements 191 to 196 are transistors in general. The leakage current of the transistor tends to become higher as the voltage between drain and sources becomes higher.
FIG. 2 is a graph showing a general relation between a brightness and applied voltage of the liquid crystal display cell (in a normally white mode). A vertical axis is brightness L. The brightness L=1 is white, and L=0 is a black. A horizontal axis is a voltage V applied to the liquid crystal cell 111. It is assumed that the voltage change of the picture signal written in the data line 121 should be stable. The change ratio (ΔL2/ΔV2) of the brightness in the halftone of the gradation is larger than the change rate (ΔL1/ΔV1, ΔL3/ΔV3) of the brightness in other gradation. Therefore, when the voltage of the picture signal in the halftone of the gradation is applied, the change of the picture signal voltage leads to remarkable enlargement of the change of brightness. Therefore, the unevenness in the display becomes highly visible.
FIG. 3 is graphs showing the change of the brightness of the driving circuit in the conventional display panel. FIG. 3(a) shows the drive voltages (the picture signal voltages) and their voltage changes. Here, the drive voltages (the picture signal voltages) are respectively applied to the data lines D1 to D6 by the six time-sharing drive. The voltage changes is the changes of voltage in the data lines when the data lines are in the non-selection state and maintain the written picture signal voltage after the driving. A vertical axis indicates elapsed time, and a horizontal axis indicates the picture signal voltage (the applied voltage). A line chart is described for each data line D1 to D6. FIG. 3(b) shows the relation between the brightness and the applied voltage of the liquid crystal cell. A vertical axis indicates the brightness L and a horizontal axis indicates the voltage of the picture signal (the applied voltage). FIG. 3(c) shows the change of the brightness of the liquid crystal cell according to the voltage change of the maintained picture signal voltage (the applied voltage) in each data line. A vertical axis indicates the brightness L and a horizontal axis indicates the data line. The liquid crystal cell in this example is operated in normally white mode.
Here, a following operation shown in FIG. 3(a) is assumed as an example. That is, at t=t0, a picture signal R1 having the applied voltage V2 of the highest gradation is written in the data line D1. At t=t1, a picture signal G1 having the applied voltage V1 of halftone is written in the data line D2. At t=t2, a picture signal B1 having the applied voltage V2 of the highest gradation is written in the data line D3. Then, at t=t3 to t5, the same signal pattern of the data lines D1 to D3 are repeated to the data lines D4 to D6 for wiring of the picture signals.
As shown in FIG. 3(a), in a data line D2 selection term (that is, “D2”: t=t1 to t2), the voltage V2 (the applied voltage) written in the data line D1 becomes in a maintenance state. However, the voltage of the data line D1 is changed by a leakage current of a switching element 191, being gradually pulled to the voltage V1 that is the writing voltage of the data line D1. In a data line D3 selection term (that is “D3”: t=t2 to t3), the voltage of the data line D2 is changed by a leakage current of a switching element 192, being gradually pulled to the voltage V2 that is the writing voltage to the data line D3. At this time, the voltage of the data line D1 tries to return the voltage V2 that is an original writing voltage. However, the voltage between the drain and source of the switching element 191 is smaller than that at the data line D2 selection term. Therefore, the voltage of the data line D1 does not return to the voltage V2 enough. Thus, the difference is larger between the writing voltage of the following data line selection term (the applied voltage) and the maintenance voltages that has already been written, the more the voltage change in the data line grows. Moreover, the voltage change becomes larger according to the enlargement of the maintenance time. Here, the maintenance time is the time period after writing in the data line to turning off the pixel transistor 112. Therefore, the change of brightness becomes large according to the enlargement.
In this way, in the six time-sharing drive of the conventional technique, for instance, in the case that the picture signal with halftone at the same level V1 in the lines D2 and D5, the voltage change in the data line D2 becomes larger than that in the data line D5. Therefore, the brightness of the liquid crystal cell by the data line D2 is different from that by the data line D5. Especially, in the case of the halftone, as shown in FIGS. 3(a) and 3(b), the brightness is greatly different even if the voltage change is slight. Then, as shown in FIGS. 3(b) and 3(c), the brightness changes ΔLD2 larger than the original brightness in the case of the liquid crystal cell of the data line D2. Also, the brightness changes ΔLD5 larger (ΔLD2>ΔLD5) than the original brightness in the case of the liquid crystal cell of the data line D5.
Generally, RGB pixels are arranged in the shape of stripe in a color liquid crystal display panel. In this case, the data lines D2 and D5 execute the displaying of G color. At this time, in the case of displaying a picture by the combination of the white level and the halftone level as shown in FIG. 3, the color is changed in each adjoining RGB pixels. It is obvious that these changes never occur in the display by the same picture signal voltage in three colors of RGB. The above-mentioned change of the maintenance voltage becomes more remarkable as the number of the time-sharing drive increases in order to downsizing of the chip in the driver IC. Because the difference of the maintenance times after the writing in the same data line array becomes large. Thus, if the brightness unevenness is seen between the data lines, it is recognized as the vertical unevenness as an entire display. As a result, the picture quality may acutely decreases.
The technique is desired, which reduces factors of the decrease of the picture quality and achieves a high-resolution picture. Also, the technique is desired, which reduces the brightness unevenness such as the vertical unevenness. Also, the technique is desired, which reduces the brightness unevenness between the data lines. Also, the technique is desired, which maintains the voltage of the picture signal in the data lines stably. Also, the technique is desired, which restricts the leakage current in the data lines.
In conjunction with the above-mentioned technique, Japanese Laid Open Patent Application (JP-A 2002-149125) discloses a data line driving circuit of the panel display. The data line driving circuit of this panel display includes a selection means, an analog buffer, a distribution means, a pre-charge means, and a control means. The selection means receives a plurality of voltages that corresponds respectively to each of a plurality of data lines in lots of data lines of the panel display. The analog buffer is commonly provided to a plurality of the data lines that receive the voltage that is selected by the selection means selectively to output. The distribution means receives the output from the analog buffer to distribute it to the one of the plurality of data lines selectively. The pre-charge means is provided to each of the lots of the data lines respectively. And the pre-charge means executes a pre-charge of the corresponding data line on any one of high drive voltage or low drive voltage according to the at least the first bit signal of the digital data corresponding to the corresponding data line. The control means controls the selection means, the distribution means and the pre-charge means. A scanning line selection term includes a pre-charge term and a plurality of writing term following. Then, in each scanning lines selection term, the control means controls the distribution means so as to separate an output of the analog buffer from all of the plurality of data line in the pre-charge term. The control means operates all the pre-charge means to pre-charge all the plurality of data lines. In the plurality of writing terms, the control means lets all of the pre-charge means a non-operation state. The control means operates the selection means and the distribution means such that the voltage corresponding to the first data line in the plurality of data lines is supplied to the analog buffer and the output of the analog buffer is supplied to the first data line in a first writing term within the plurality of writing terms. Also, in the second writing term within the plurality of writing terms, the voltage corresponding to the second data line in the plurality of data lines is supplied to the analog buffer, and the output of the analog buffer is supplied to the second data line.
In conjunction with the above-mentioned technique, Japanese Laid Open Patent Application (JP-A-Heisei 11-133462) discloses a liquid crystal device and an electronic device. In the liquid crystal device, a liquid crystal is held being sandwiched by a couple of substrates. One substrate of the couple of substrates includes a pixel electrode, a seal material, and a shading member. The pixel electrodes is formed in matrix. The seal material surround the liquid crystal sandwiching the couple of substrates in surroundings of the screen region, which is defined by the plurality of pixel electrodes on the one substrate. The shading member is formed on the another substrate of the couple of substrates along an outline of the display region between the seal material and the display region. The peripheral circuit is formed of a thin film transistor. The driver circuit is arranged on the one substrate in the counter position of the shading member which is formed on the another substrate.